FIG. 1A shows an underside plan view of a conventional quad flat no-lead (QFN) package utilized to house a semiconductor device. FIG. 1B shows a cross-sectional view taken along line B-B′, of the conventional QFN package of FIG. 1A, positioned on a PC board.
QFN package 100 comprises semiconductor die 102 having electrically active structures fabricated thereon. Die 102 is affixed to underlying diepad 104a portion of lead frame 104 by adhesive 106. The relative thickness of the die and lead frame shown in FIG. 1B, and all other drawings of this patent application, is not to scale. Lead frame 104 also comprises non-integral pin portions 104b in electrical communication with die 102 through bond wires 108. Bond wires 108 also allow electrical communication between die 102 and diepad 104a. 
Plastic molding 109 encapsulates all but the exposed portions 104a′ and 104b′ of the lead frame portions 104a and 104b, respectively. For the purposes of this patent application, the term “encapsulation” refers to partial or total enveloping of an element in a surrounding material, typically the metal of the lead frame within a surrounding dielectric material such as plastic.
Portions of the upper surface of lead frame 104 bear silver Ag 105 formed by electroplating. The lower surface of lead frame 104 bears a layer of Pd/Ni or Au/Ni 107 formed by electroplating.
QFN package 100 is secured to traces 110 of underlying PC board 112 by solder 114 that preferably has the rounded shape indicated. The electrically conducting properties of solder 114 allows electrical signals to pass between lead frame portions 104a and 104b and the underlying traces 110.
FIG. 1C shows a plan view of only the lead-frame 104 of QFN package 100 of FIGS. 1A-B. Lead frame 104 is typically formed by etching a pattern of holes completely through a uniform sheet of copper. FIG. 1D shows one example of such a pattern of holes 116 in a copper roll 118. These patterns of holes define a proto-lend frame 122 comprising proto-diepad 124 and proto-non-integral portions 126. Proto-diepad 124 is secured to the surrounding metal frame by tie bars 120. Proto-non-integral pin portions 126 are secured to the surrounding metal frame by tabs 128.
The patterned metal portion shown in FIG. 1D is processed into a package by gluing a die to the diepad, and connecting bond wires between the die and non-integral portions and/or the diepad. While the diepad and non-integral portions are still attached to the surrounding metal, the bond wires and a portion of the diepad and non-integral lead frame portions are encapsulated within a dielectric material such as plastic. Fabrication of an individual package is then completed by severing the tabs and tie bars to singulate an individual package from its surrounding metal frame and other packages associated therewith.
While adequate for many purposes, the conventional QFN package just described offers some drawbacks. One drawback is the difficulty of forming raised features on the lead frame.
For example, FIG. 1B shows that non-integral lead frame pin portions 104b exhibit a thinned region 104b″ proximate to the diepad. Thinned pin region 104b″ is surrounded on three sides by the plastic encapsulant 109 of the package body, thereby physically securing non-integral pin portion 104b within the package.
Moreover, FIG. 1B also shows that diepad portions 104a exhibit a thinned region 104a″ proximate to the non-integral pins. Thinned diepad region 104a″ is surrounded on three sides by the plastic encapsulant of the package body, thereby physically securing the diepad within the package.
FIGS. 1E-1H show cross-sectional views of the conventional process steps for fabricating a lead frame having a thinned portion. In FIG. 1E, the inverted Cu sheet 118 is electroplated on its bottom surface with an Au/Pd/Ni combination or an Ag/Ni combination to form layer 107. For the Au/Pd/Ni combination, the Au is between about 0.01-0.015 μm in thickness, the Pd is between about 0.02-0.2 μm in thickness, and the Ni is between about 0.5-2.5 μm in thickness. For an Ag/Ni electroplated coating, Ag and Ni are each between about 0.5-2.5 μm in thickness.
In FIG. 1F, photoresist mask 150 is patterned over layer 107 to expose the regions 152 that are to be thinned. Exposed regions 152 are then exposed to an etchant for a controlled period, which removes Cu material to a predetermined depth Y.
In FIG. 1G, the photoresist mask is removed, and Cu roll 118 is then reoriented right side up. The upper surface of the Cu roll 118 is then selectively electroplated to form silver layer 105. The silver may be electroplated only in specific regions over the substrate utilizing a mask (not shown) during this step.
In FIG. 1H, the backside of partially-etched Cu sheet 118 is patterned with a photoresist mask 119 leaving exposed areas 121 corresponding to the thinned regions. The partially-etched Cu sheet 118 is then etched completely through in the exposed areas 121 to form a pattern of holes 116 separating diepad 104a from non-integral pins 104b. 
Fabrication of the QFN package is subsequently completed by affixing the die to the diepad, attaching bond wires between the die and diepad and non-integral pin portions, and then enclosing the structure within plastic encapsulation, as is well known in the art.
The etching stage of the QFN package fabrication process shown in FIG. 1F is relatively difficult to control with precision. Specifically, the accuracy of etching the Cu lead frame in small areas is about 20-25% of the total lead frame thickness. This is due to inability to rapidly and reproducibly halt the progress of chemical etching reaction once it is initiated. Etching outside the above tolerance range can result in the scrapping of many lead frames, elevating package cost.
Moreover, the conventional approach of partial etching to shape thinned features limits the pitch of the lead, and thus the number of pins available for a given QFN package body size. This limitation in lead pitch results from the at least partially isotropic character of the etching process, which removes material in the lateral, as well as vertical, direction.
Therefore, there is a need in the art for improved techniques for fabricating semiconductor device packages.